1. Field of the Invention
The present invention generally concerns recovery of timing signals, and in particular concerns the recovery of a clock signal from an incoming stream of Coded Marked Inversion (CMI) data.
2. Background Information
In applications relating to the transmission of digital data, for example, across a communications cable, the format of the transmitted signal is always important, since the circuitry in the receiver must be able to extract precise timing information from the incoming signal. Three main purposes of the timing extraction are to allow the signal to be sampled by the receiver at the time the signal-to-noise ratio is a maximum, to maintain the proper pulse spacing, and to indicate the start and end of each timing interval. In addition, since errors resulting from noise and distortion can occur in the signal detection process, it may be desirable for the signal to have an inherent error-detection property. One such signal format that provides these features is the well-known Coded Marked Inversion (CMI) format.
The CMI format is a two-level line code in which each bit of the digital data is converted into a pair of data tokens. An example of a stream of digital data being converted form the Non-Return-to-Zero (NRZ) format to the CMI format is shown in
FIG. 1. Specifically, a data bit of xe2x80x9c0xe2x80x9d is converted into a pair of data tokens xe2x80x9c0,1xe2x80x9d, and a data bit of xe2x80x9c1xe2x80x9d is converted alternatively into a pair of data tokens xe2x80x9c0,0xe2x80x9d and xe2x80x9c1,1xe2x80x9d. The pair of data tokens xe2x80x9c1,0xe2x80x9d is, by definition, an illegal combination. The converted pairs of data tokens, i.e., xe2x80x9c0,1xe2x80x9d, xe2x80x9c0,0xe2x80x9d, or xe2x80x9c1,1xe2x80x9d, is transmitted within the same time frame (period P) in which the digital data is applied to the encoding unit.
CMI is an encoding scheme adopted by SONET STS-3 and SDH STM1 standards, among other standards. CMI encoding guarantees at least one transition per bit, thereby enhancing the clock recovery process at the expense of extra signal bandwidth consumed. Accordingly, all 0s can be regarded as normal CLK frequency, and all 1s can be visualized as half the CLK frequency.
In the prior art, frequency multipliers have been used to double the clock edges for phase comparison. However, it is difficult to implement accurate frequency multipliers at very high bit rates that are common to modern high-speed communication systems. Additional prior art schemes, such as that disclosed in U.S. Pat. No. 5,195,110, implement circuitry that is more complex than desired. Accordingly, it would be advantageous to provide an improved approach that does not require accurate frequency multipliers, and is simpler than schemes found in the prior art.